Integrated circuit chips or semiconductor devices typically undergo testing to verify their operability under a variety of conditions by their manufacturer. Generally, these chips are tested by automatic test equipment called an integrated circuit tester. The integrated circuit tester is colloquially referred to as a “tester.” Chips are tested for a variety of reasons. For example, the tester may be used for sorting out faulty chips or for grading the chips on performance characteristics. In addition, a tester may be used during manufacture to guide the repair of chips that are defective. A chip that is being tested is commonly referred to as a device under test (DUT).
Generally testers include a host computer that runs software for controlling various tests on the DUT. Moreover, traditional testers contain numerous “channels” or “pins.” Channel circuits typically include a driver circuit to generate test signals and/or a detector circuit or comparator circuit to measure output signals. To test a DUT, selected leads, pins or ports on the DUT are coupled to selected channels of the tester. In a typical testing scenario, one or more of the channels is programmed to simulate an input to the chip. Moreover, a receiver in one or more channels is also programmed to detect one or more expected outputs.
Traditionally, single ended channels were used in the testers because single-ended signals were traditionally used in chips. A single-ended signal comprises a single signal for conveying a digital logic state with reference to a digital ground. A single-ended signal is detected as having a high logic level, a low logic level or a logic state between a high and a low logic level (a “between” state). Problems can arise with single-ended signals during high speed operations due to interference from ground bounce, noise and cross talk.
Some modem chips running at high speeds use differential circuits to generate differential signals to convey logic states. These chips employ differential signal ports. Differential signals convey a digital logic state as differences between two signals, neither one of which is ground. The effects of ground bounce, noise and cross talk are less on high speed systems incorporating differential signals than those systems incorporating single-ended signals. Typically, a differential amplifier is used to compare the differential margin of the signals in determining the logic level. There is a need in the art for a tester that effectively tests a DUT having differential signal ports.
The channel circuitry of testers can also be programmed to generate or check for an expected signal at a precise time. For example, most chips are clocked. That is, most integrated circuits have a clock input that changes states on a periodic basis. Generally, a chip latches a set of input signals at a set time in relation to a change in the clock signal. If valid data signals are not applied to the chip at the change in the clock signal, the chip will latch improper data.
Traditionally, a common clock was used for every chip inside an electronic system. Using a common clock allows each chip to produce its output and latch its input in association with other chips in the electronic system. However, problems can occur with the common clock system when signals move through one part of the electronic system at a different rate than other parts of the electronic system. The differences in time are sometimes called “skew.” When designing a system, the skew must be taken into account. Typically, the faster the electronic system, the more difficult it is to design to compensate for the skew.
More recently, a new clocking architecture has been used in systems that need to process many operations per second. This architecture is sometimes referred to as “source synchronous,” “clock forwarding” or “echo clocks.” In a source synchronous architecture, each chip in an electronic system that produces output signals (data signals) also produces an output clock signal (data clock signal). The data clock signal is fed to other chips in the electronic system along with the data signals. The other chip uses the data clock signal input to latch the input data signals. Because the data clock signal and the data signals travel over similar paths, there is less skew between the data signals and the data clock signal than between the data signals and the common clock. There is a need in the art for a tester that can effectively test DUT's having a source synchronous architecture.
Another problem with testing source synchronous systems relates to the speed of the data processed by the system. Specifically, source synchronous systems operate in a different, independent time domain compared to the tester. As systems increase in speed, it becomes more difficult to align the different time domains of the DUT and the tester. This in turn makes comparison of data read from the DUT with expected data more complicated and prone to error since measurements may be taken at the wrong time due to the dual time domains.
For the reasons state above and for the reasons stated below, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a tester that can effectively test DUT's having differential signal ports and source synchronous architecture especially in light of the increasing speed of some systems.